Integrated semiconductor assemblies and methods of manufacturing the same

ABSTRACT

Integrated semiconductor assemblies and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device assembly comprises a base substrate having a cavity and a perimeter region at least partially surrounding the cavity. The cavity is defined by sidewalls extending at least partially through the substrate. The assembly further comprises a first die attached to the base substrate at the cavity, and a second die over at least a portion of the first die and attached to the base substrate at the perimeter region. In some embodiments, the first and second dies can be electrically coupled to each other via circuitry of the substrate.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of U.S. patent application Ser. No.15/683,609, filed Aug. 22, 2017, which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

The present technology is directed to packaging semiconductor devices,such as memory and processors, and several embodiments are directed tointegrated semiconductor assemblies including substrates havingcavities.

BACKGROUND

Packaged semiconductor dies, including memory dies, microprocessor dies,and interface dies, typically include a semiconductor die mounted on asubstrate and encased in a plastic protective covering. The die includesfunctional features, such as memory cells, processor circuits, andinterconnecting circuitry, as well as bond pads electrically connectedto the functional features. The bond pads are often electricallyconnected to external terminals that extend outside of the protectivecovering to allow the die to be connected to busses, circuits or otherhigher level circuitry.

Semiconductor die manufacturers are under increasing pressure tocontinually reduce the size of die packages to fit within the spaceconstraints of electronic devices, while also increasing the functionalcapacity of each package to meet operating parameters. One approach forincreasing the processing power of a semiconductor package withoutsubstantially increasing the surface area covered by the package (i.e.,the package's “footprint”) is to vertically stack multiple semiconductordies on top of one another in a single package. Stacking multiple dies,however, increases the vertical profile of the device, requiring theindividual dies to be thinned substantially to achieve a verticallycompact size. Additionally, the stacking of multiple dies can increasethe probability of device failure, and lead to higher costs associatedwith longer manufacturing and testing times.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic cross-sectional view of a semiconductor deviceassembly configured in accordance with an embodiment of the presenttechnology.

FIG. 1B is a schematic top view of the semiconductor device assemblyshown in FIG. 1A taken along line 1B-1B.

FIGS. 2A-2C are schematic cross-sectional views illustrating a method offorming a semiconductor device assembly in accordance with an embodimentof the present technology.

FIG. 3 is a schematic top view of a semiconductor device assemblyconfigured in accordance with another embodiment of the presenttechnology.

FIGS. 4-7 are schematic cross-sectional views of semiconductor deviceassemblies configured in accordance with other embodiments of thepresent technology.

FIG. 8 is a schematic view of a system that includes a semiconductor dieassembly configured in accordance with embodiments of the presenttechnology.

DETAILED DESCRIPTION

Specific details of several embodiments of stacked semiconductor diepackages and methods of manufacturing such die packages are describedbelow. The term “semiconductor device” generally refers to a solid-statedevice that includes semiconductor material. A semiconductor device caninclude, for example, a semiconductor substrate, wafer, or die that issingulated from a wafer or substrate. Throughout the disclosure,semiconductor devices are generally described in the context ofsemiconductor dies; however, semiconductor devices are not limited tosemiconductor dies.

The term “semiconductor device package” can refer to an arrangement withone or more semiconductor devices incorporated into a common package. Asemiconductor package can include a housing or casing that partially orcompletely encapsulates at least one semiconductor device. Asemiconductor device package can also include an interposer substratethat carries one or more semiconductor devices and is attached to orotherwise incorporated into the casing. The term “stacked packageassembly” can refer to an assembly of one or more individualsemiconductor device packages stacked on each other or apackage-on-package assembly.

As used herein, the terms “vertical,” “lateral,” “top,” “bottom,”“upper,” and “lower” can refer to relative directions or positions offeatures in the semiconductor device or package in view of theorientation shown in the Figures. For example, “upper” or “outermost”can refer to a feature positioned closer to the top of a page thananother feature. These terms, however, should be construed broadly toinclude semiconductor devices having other orientations, such asinverted or inclined orientations where top/bottom, over/under,above/below, up/down, vertical/horizontal and left/right can beinterchanged depending on the orientation.

FIG. 1A is a schematic cross-sectional view of a semiconductor deviceassembly 100 (“assembly 100”) configured in accordance with anembodiment of the present technology, and FIG. 1B is a schematic topview of the assembly 100 shown in FIG. 1A taken along line 1B-1B. Theassembly 100 shown in FIG. 1A is taken along line 1A-1A of FIG. 1B.Referring to FIGS. 1A and 1B together, the assembly 100 includes a basesubstrate 110, a first die 120 mounted to the substrate 110, and asecond die 130 mounted to the substrate 110. The substrate 110 includesa first side 111 a, a second side 111 b opposite the first side 111 a, acavity 115 at the first side 111 a, and one or more power and/or signallayers 117 having circuitry (e.g., copper traces and vias) forelectrically coupling the first and second semiconductor dies 120, 130to each other, other electrical devices, and/or electrical connectors116 (e.g., solder balls, gold fingers, or other interconnections). Thesubstrate 110, for example, can be a printed circuit board (PCB) orother type of substrate commonly used in semiconductor device packages.In some embodiments, the substrate 110 can be formed at least in partfrom silicon. The substrate 110 includes a cavity region (C) and aperimeter region (P) at least partially surrounding the cavity region(C). As such, the substrate 110 includes a continuous outermost surfaceincluding at least an upper surface 112 a of the perimeter region (P), alower surface 112 b of the cavity region (C), and sidewalls 128. In theillustrated embodiment, the perimeter region (P) completely surroundsthe cavity region (C).

The cavity 115 is positioned in the cavity region (C) of the substrate,and is defined by the sidewalls 128 and the lower surface 112 b. Thesidewalls 128 extend at least partially through the substrate 110 to anintermediate depth, or a second distance (D₂). In some embodiments, thesidewalls 128 can extend through the substrate 110 from the first side111 a to the second side 111 b. In the illustrated embodiment of FIG.1B, the cavity 115 is positioned entirely within the substrate 110 andthus includes four sidewalls 128. In other embodiments, the cavity 115can extend to or beyond a length or width of the substrate 110 andtherefore may only include two sidewalls 128 (e.g., FIG. 3). Althoughthe cavity 115 illustrated in FIGS. 1A and 1B has a rectilinear planwith four sidewalls, in other embodiments a cavity can have any one of anumber of other shapes, including regular polygons with any number ofsides, irregular polygons, ellipses or curvilinear shapes, etc.

The first die 120 is positioned within the cavity 115 and includes a topsurface 121 a and a bottom surface 121 b opposite the top surface 121 a.The first die 120 is attached to the base substrate 110 via a pluralityof electrical connectors 122 (e.g., solder balls, bond pads, etc.) atthe bottom side 121 b. The top surface 121 a is separated from the lowersurface 112 b of the cavity 115 by a first distance (D₁). In theillustrated embodiment, the first distance (D₁) is less than the seconddistance (D₂) previously described. Accordingly, the first die 120 ispositioned entirely within the cavity 115 such that the top surface 121a of the first die 120 is below the upper surface 112 a of the perimeterregion (P) of the substrate 110. In other embodiments, the firstdistance (D₁) can be equal to (e.g., FIGS. 2A-2C) or slightly greaterthan the second distance (D₂). The first die 120 can include a memorydevice or memory module (e.g., DRAM, LPDRAM, SRAM, DIMM, NVDIMM, RDIMM,LRDIMM, Flash, etc.). In some embodiments, the first die 120 can includea logic device and/or processor.

The illustrated embodiment of FIG. 1A includes only a single die. Insome embodiments, additional dies may be included in the cavity 115. Forexample, a stack of dies in the cavity 115 can be configured as a hybridmemory cube (HMC) in which the lowermost die is a logic die thatprovides memory control (e.g., DRAM control), and the stacked dies overthe lowermost die are DRAM or other memory dies that provide datastorage. In such an embodiment, a top surface of the outermost die ofthe stack is below a bottom surface of the second die 130.

The second die 130 is positioned over a portion of the first die 120 andincludes a top surface 137 a and a bottom surface 137 b. As such, thesecond die 130 traverses the first die 120 and the cavity region 115.The second die 130 is attached to the substrate 110 at the perimeterregion (P) via electrical connectors 132 (e.g., solder balls, bond pads,etc.). The electrical connectors 132 can electrically couple the seconddie 130 to (i) the substrate 110 and/or (ii) the first die 120 via thesubstrate 110. In the illustrated embodiment, the second die 130includes a larger lateral dimension than that of the cavity 115 and thefirst die 120. The bottom surface 137 b of the second die 130 is spacedapart from the lower surface 112 b of the cavity region (C) by a thirddistance (D₃). The third distance (D₃) is larger than each of the firstdistance (D₁) and the second distance (D₂). The second die 130 can be alogic device, processor, or another memory device. Optionally, theassembly 100 can also include electrical connectors 140 (e.g., solderballs, bond pads, etc.) between the first and second dies 120, 130. Insuch an embodiment, the electrical connectors 140 electrically couplethe first die 120 directly to the second die 130.

One benefit of the present technology is the decreased thickness of theassembly 100 achieved by mounting the first die 120 within the cavity115 and/or below the second die 130. Because the first die 120 ismounted within the cavity 115, the second die 130 can be mounted overthe first die 120 and proximate the upper surface 112 a of thesubstrate, thereby decreasing the thickness of the overall assembly. Asmentioned previously, stacked devices have higher probabilities ofdevice failure and higher costs associated with longer manufacturing andtesting times. Accordingly, assemblies including the present technologycan result in higher yields, more efficient manufacturing, and decreasedcosts.

Another benefit of the present technology is the ability to moreefficiently dissipate heat from the first die 120 and/or the second die130. Unlike conventional stacked devices wherein multiple dies arestacked directly over one another, the present technology includes airgaps between the first and second dies 120, 130 thereby allowing bothdies to cool via convection to the surrounding environment. Accordingly,the assembly 100 can maintain a lower average operating temperaturecompared to a stacked device, resulting in more efficient operation andlonger run times.

Yet another benefit of the present technology is the positioning of thesecond die 130 relative to the first die 120. In conventional stackedassemblies, the processor is often the main heat-generating source andis usually positioned proximate the substrate at the bottom of thestack. This is in part because the processor usually includes thelargest lateral dimension relative to the other dies of the stack. Thistype of arrangement causes heat to become trapped at the bottom of thestack, and results in an overall increased operating temperature for theassembly. Unlike conventional stacked assemblies, the second die 130 ofthe present technology can include a processor and be positioned overthe first die 120. As such, any heat generated from the processor isreleased upwards toward the surrounding environment and has less thermaleffect on the first die 120 within the cavity 115. Therefore, thepresent technology can result in a lower operating temperature and moreefficient device.

FIGS. 2A-2C are schematic cross-sectional views illustrating a method offorming a semiconductor device assembly (such as or similar to theassembly 100) in accordance with an embodiment of the presenttechnology. FIG. 2A illustrates the method after the cavity 115 has beenformed in the substrate 110 and the first die 120 has been disposedwithin the cavity 115 between the sidewalls 128. The cavity 115 can beformed by grinding, dry etching, chemical etching, chemical polishing,chemical-mechanical polishing, or other suitable processes known in theart. The lateral dimension or width of the cavity may be predeterminedto ensure the first die 120 can fit within cavity 115. Similarly, thedepth of the cavity 115 may be predetermined based on the combinedheight of the first die 120 and the electrical connectors 122 beforeand/or after reflow. In the illustrated embodiment, the top surface 121a of the first die 120 is generally co-planar with the upper surface 112a of the perimeter region (P) of the substrate 110.

FIG. 2B illustrates an embodiment of the method after a mold material220 (e.g., an underfill material, encapsulant, etc.) has been depositedin the cavity 115 to encapsulate the first die 120. In the illustratedembodiment, an outer surface of the mold material 220 is flush with theupper surface 112 a of the perimeter region (P) of the substrate 110.Thus, in the illustrated embodiment, the mold material 220 onlypartially encapsulates the first die 120 because the top surface 121 aof the first die 120 is generally co-planar with the upper surface 112 aof the perimeter region (P) and is thus exposed through the moldmaterial 220. In other embodiments, the top surface 121 a of the firstdie 120 is below the upper surface 112 a (e.g., FIGS. 1A and 1B). Insuch an embodiment, the top surface 121 a is not exposed through themold material 220, and thus the mold material 220 completelyencapsulates the first die 120. In other embodiments, the mold material220 can be omitted.

FIG. 2C illustrates an embodiment of the method after the second die 130is disposed over at least a portion of the first die 120 and/or thecavity 115 and mounted to the substrate 110 at the perimeter region (P).The second die 130 can be electrically coupled to the first die viacircuitry of the substrate 110. As previously described with referenceto FIG. 1A, in some embodiments, the method can further includedepositing electrical connectors (not shown) between the first andsecond dies 120, 130 prior to disposing the second die 130 on thesubstrate 110. In such an embodiment, the electrical connectors couplethe first die 120 directly to the second die 130. As described infurther detail below with reference to FIGS. 3 and 4, the method canfurther include disposing a third die on the substrate 110 that isstacked on or spaced apart from the second die 130.

FIG. 3 is a schematic top view of a semiconductor device assembly(“assembly 300”) configured in accordance with another embodiment of thepresent technology. The assembly 300 is generally similar to theassembly 100 previously described. For example, the assembly 300includes the substrate 110 having a cavity 315 with the first die 120positioned therein. The assembly 300 includes a cavity region (C) and aperimeter region (P) that only partially surrounds the cavity region(C). The assembly 300 further includes a second die 330 and a third die335 each attached to the substrate 110 at the perimeter region (P). Thesecond die 330 includes a top surface 331 a and a bottom surface 331 bopposite the top surface 331 a. The bottom surface 331 b is attached tothe substrate 110 via electrical connectors 132. The third die 335includes a top surface 336 a and a bottom surface 336 b opposite the topsurface 336 a. The bottom surface 336 b is attached to the substrate 110via electrical connectors 132. The second and third dies 330, 335 eachtraverse a different portion of the first die 120.

FIG. 4 is a schematic cross-sectional view of a semiconductor deviceassembly 400 (“assembly 400”) configured in accordance with anotherembodiment of the present technology. The assembly 400 is generallysimilar to the assembly 100 previously described. For example, theassembly 400 includes the substrate 110 having the cavity 115, the firstdie 120 positioned in the cavity 115, and the second die 130 over thefirst die 120 and attached to the substrate 110 at the perimeter region(P). The assembly 400 includes a third die 430 stacked on and attachedto the second die 130. The third die 430 can be electrically coupled tothe second die 130 via a plurality of electrical connectors (e.g.,solder balls, wirebonds, etc.). In other embodiments, the third die 430can be attached and electrically coupled to the second die 130 via othermeans including interconnects, die attach films, TSVs, and/or otherknown methods in the art. A person of ordinary skill in the art willunderstand that additional dies can be stacked over the third die 430and/or on the substrate 110.

FIG. 5 is a schematic cross-sectional view of a semiconductor deviceassembly 500 (“assembly 500”) configured in accordance with anotherembodiment of the present technology. The assembly 500 is generallysimilar to the assembly 100 previously described. For example, theassembly 500 includes the substrate 110 having the cavity 115, the firstdie 120 positioned in the cavity 115, and the second die 130 over thefirst die 120 and attached to the substrate 110 at the perimeter region(P). The assembly 500 includes a second cavity 515 at the second side111 b of the substrate 110, a third die 520 positioned in the cavity 515and attached to the substrate 110, and a fourth die 530 traversing thethird die 520 and attached to the substrate 110 at the perimeter region(P) via bond pads 532. The bond pads 532 can further decrease thethickness of the assembly 500 compared to a die attached to thesubstrate with solder balls or the like. The third die 520 and/or thefourth die 530 can be electrically coupled to the first die 120 and/orthe second die 130 via circuitry of the substrate 110. The arrangementof the second cavity 515, third die 520, and fourth die 530 at thesecond side 111 b can be similar or identical to the arrangement of thefirst cavity 115, first die 120, and second die 130 at the first side111 a. As such, the features and benefits previously described withreference to assembly 100 and FIGS. 1A-1B, also apply to the assembly500. In some embodiments, the fourth die 530 can be omitted from theassembly 500. In such an embodiment, the assembly 500 may includeelectrical connectors (e.g., electrical connectors 116 from FIG. 1A)over the perimeter region (P) at the second side 111 b of the substrate110. The assembly 500 may also include electrical connections, such asedge fingers, interconnection sockets, and other similar structurescommonly found on PCBs.

FIG. 6 is a schematic cross-sectional view of a semiconductor deviceassembly 600 (“assembly 600”) configured in accordance with anotherembodiment of the present technology. The assembly 600 includes featuresgenerally similar to the assembly 100 previously described. For example,the assembly 600 includes the substrate 110 having the cavity 115, andthe second die 130 attached to the substrate 110 at the perimeter region(P). The assembly 600 includes a first die 620 including a first surface627 a facing the second die 130, and a second surface 627 b opposite thefirst surface 627 a and facing the substrate 110. The first die 620 canbe attached to the second die 130 via an adhesive tape, die attach film,bond pads, or other methods known in the art. The first die 620 is atleast partially within the cavity 115 such that a portion of the firstdie 620 is between the sidewalls 128 and/or below the upper surface 112a. In the illustrated embodiment, for example, the second surface 627 bis lower than the upper surface 112 a. The first die 620 can beelectrically coupled to the second die 130, and to the substrate 110 viathe second die 130 and electrical connectors 132. The first die 620 caninclude features similar or identical to the first die 120 previouslydescribed. The assembly 600 can optionally include a third die 650attached to the second die 130 at the top side 137 a. The third die 650can include features similar or identical to the first or second dies120, 130 previously described. The assembly 600 can be formed via asimilar method as described with reference to FIGS. 2A and 2C, exceptthat the first die 620 is attached to the second die 130 before thesecond die is attached to the substrate 110. The third die 650 can beattached to the second die 130 before or after the first die 620 isattached to the second die 130.

FIG. 7 is a schematic cross-sectional view of a semiconductor deviceassembly 700 (“assembly 700”) configured in accordance with anotherembodiment of the present technology. The assembly 700 includes a firstdie 720 a and a second die 720 b that are between the sidewalls 128 andattached to the substrate 110 at the cavity 115 via electricalconnectors 122. The first and second dies 720 a-b can each includefeatures generally similar to those of the first die 120 previouslydescribed. The assembly 700 further includes a third die 730 a, a fourthdie 730 b, and a fifth die 730 c over at least a portion of either thefirst and/or second dies 720 a-b. The third, fourth, and fifth dies 730a-c can each include features general similar to those of the second die130 previously described. The third die 730 a and the fifth die 730 care each attached to the base substrate via electrical connectors 132with a first portion of the electrical connectors 132 attached directlyto the perimeter region (P) at the upper surface 112 a of the substrate110, and a second portion of the electrical connectors 132 attacheddirectly to a top surface 721 a of the first die 720 a. As such, thethird die 730 a and the fifth die 730 c extend over only a portion of(a) the cavity 115 and (b) the first die 720 a or second die 720 brespectively. The fourth die 730 b is attached directly to the first andsecond dies 720 a-b via electrical connectors 132, with a first portionof the electrical connectors 132 attached to the top surface 721 a ofthe first die 720 a and a second portion of the electrical connectors132 attached to the top surface 721 b of the second die 720 b. As such,the fourth die 730 b is positioned over the cavity 115 and between thesidewalls 128. In some embodiments, the third, fourth and/or fifth dies730 a-c may be omitted. For example, the assembly 700 can include onlythe fourth die 730 b or only the third and fifth dies 730 a,c.

Any one of the semiconductor devices and/or assemblies described abovewith reference to FIGS. 1A-7 can be incorporated into any of a myriad oflarger and/or more complex systems, a representative example of which issystem 890 shown schematically in FIG. 8. The system 890 can include asemiconductor assembly 800 (“assembly 800”), a power source 892, adriver 897, a processor 896, and/or other subsystems or components 898.The assembly 800 can include features generally similar to thoseassemblies described above. The resulting system 890 can perform any ofa wide variety of functions, such as memory storage, data processing,and/or other suitable functions. Accordingly, representative systems 890can include, without limitation, hand-held devices (e.g., mobile phones,tablets, digital readers, and digital audio players), computers, andappliances. Components of the system 890 may be housed in a single unitor distributed over multiple, interconnected units (e.g., through acommunications network). The components of the system 890 can alsoinclude remote devices and any of a wide variety of computer readablemedia.

This disclosure is not intended to be exhaustive or to limit the presenttechnology to the precise forms disclosed herein. Although specificembodiments are disclosed herein for illustrative purposes, variousequivalent modifications are possible without deviating from the presenttechnology, as those of ordinary skill in the relevant art willrecognize. For example, the illustrated embodiments of FIG. 4, whichincludes stacked devices, and FIG. 5, which includes multiple cavitiesand dies positioned therein, can be combined or incorporated into otherembodiments, such as the illustrated embodiment of FIG. 6. In somecases, well-known structures and functions have not been shown ordescribed in detail to avoid unnecessarily obscuring the description ofthe embodiments of the present technology. For example, a person ofordinary skill in the art will understand that the dies previouslydescribed can include a plurality of passive components, such asresistors, capacitors, and/or other types of electrical devicesincorporated therein. Although steps of methods may be presented hereinin a particular order, alternative embodiments may perform the steps ina different order. Similarly, certain aspects of the present technologydisclosed in the context of particular embodiments can be combined oreliminated in other embodiments. Furthermore, while advantagesassociated with certain embodiments of the present technology may havebeen disclosed in the context of those embodiments, other embodimentscan also exhibit such advantages, and not all embodiments neednecessarily exhibit such advantages or other advantages disclosed hereinto fall within the scope of the technology. Accordingly, the disclosureand associated technology can encompass other embodiments not expresslyshown or described herein, and the invention is not limited except as bythe appended claims.

Throughout this disclosure, the singular terms “a,” “an,” and “the”include plural referents unless the context clearly indicates otherwise.Similarly, unless the word “or” is expressly limited to mean only asingle item exclusive from the other items in reference to a list of twoor more items, then the use of “or” in such a list is to be interpretedas including (a) any single item in the list, (b) all of the items inthe list, or (c) any combination of the items in the list. Additionally,the term “comprising,” “including,” and “having” are used throughout tomean including at least the recited feature(s) such that any greaternumber of the same feature and/or additional types of other features arenot precluded. Reference herein to “one embodiment,” “an embodiment,” orsimilar formulations means that a particular feature, structure,operation, or characteristic described in connection with the embodimentcan be included in at least one embodiment of the present technology.Thus, the appearances of such phrases or formulations herein are notnecessarily all referring to the same embodiment. Furthermore, variousparticular features, structures, operations, or characteristics may becombined in any suitable manner in one or more embodiments.

1. A semiconductor device assembly comprising: a base substrate having acavity and a perimeter region at least partially surrounding the cavity,wherein the cavity extends at least partially through the base substrateand has an opening width measured across opposing edges of the perimeterregion; a first device in the cavity and attached to the base substrateat the cavity; and a second device over at least a portion of the firstdevice, extending across the opposing edges of the perimeter region, andattached to the base substrate at the perimeter region, wherein thesecond device has a device width that is greater than the opening widthof the cavity; and wherein a top surface of the first device and abottom surface of the second device are separated by a distancecorresponding to an air channel for cooling the first and second devicesvia convection.
 2. (canceled)
 3. (canceled)
 4. The assembly of claim 1,wherein the base substrate includes a continuous outermost surfacespanning along a lower surface of the cavity and an upper surface of theperimeter region.
 5. The assembly of claim 1 wherein the perimeterregion includes an upper surface and the cavity includes a lower surfaceseparated from the upper surface by a first distance, and wherein thefirst device includes the top surface separated from the lower surfaceof the cavity by a second distance less than the first distance.
 6. Theassembly of claim 1 wherein the perimeter region completely surroundsthe cavity.
 7. The assembly of claim 1, further comprising anencapsulant at least partially encapsulating the first device, wherein atop surface of the encapsulant is below the bottom surface of the seconddevice.
 8. The assembly of claim 1, further comprising a third deviceattached to the second device, wherein the third device is over thefirst device and the second device.
 9. The assembly of claim 1 whereinthe portion of the first device is a first portion, the assembly furthercomprising a third device attached to the base substrate at theperimeter region and spaced apart from the second device, wherein thethird device is over at least a second portion of the first device. 10.The assembly of claim 1 wherein the base substrate includes a first sideand a second side opposite the first side, wherein the perimeter regionis a first perimeter region and the cavity is a first cavity, andwherein the first cavity and the first perimeter region are at the firstside of the base substrate, the assembly further comprising: a cavity atthe second side of the substrate and extending at least partiallythrough the substrate toward the first side of the substrate; and asecond perimeter region at least partially surrounding the secondcavity.
 11. The assembly of claim 10, further comprising: a third devicein the second cavity and attached to the base substrate at the secondcavity.
 12. The assembly of claim 11, further comprising: a fourthdevice over the third device and attached to the base substrate at thesecond perimeter region.
 13. The assembly of claim 1 wherein the firstdevice includes a memory chip and the second device includes a processorchip.
 14. The assembly of claim 13 wherein one or more peripheralportions of the top surface of the memory chip laterally extends pastcorresponding peripheral edges of the processor chip.
 15. The assemblyof claim 14 wherein: the processor chip and the memory chip comprise adie stack; the processor chip is located at a top portion of the diestack for releasing heat generated by the processor chip upward; and theone or more peripheral portions of the top surface of the memory chip isuncovered by the processor chip for reducing thermal effect between theprocessor chip and the memory chip.
 16. A stacked package systemcomprising: a substrate having a cavity region and a perimeter region atleast partially peripheral to the cavity region, wherein the cavityregion is defined by sidewalls extending at least partially through thesubstrate and separated by an opening width measured across opposingportions of the side walls; a first device attached to the substrate andpositioned between the sidewalls of the cavity region; and a seconddevice over the first device, extending across the opening width andover the opposing portions of the perimeter region, and attached to thebase substrate at the perimeter region, wherein the second device has adevice width that is greater than the opening width of the cavity; andwherein a top surface of the first device and a bottom surface of thesecond device are separated by a distance corresponding to an airchannel for cooling the first and second devices via convection.
 17. Thesystem of claim 16 wherein the cavity region includes a lower surfacebetween the sidewalls, and wherein the first device is attached to thelower surface via a plurality of connectors.
 18. The system of claim 16wherein the second device includes a bottom side facing at leastpartially toward the substrate and a top side opposite the bottom side,and wherein the first device is attached to the second device at thebottom side.
 19. The system of claim 16, further comprising a thirddevice attached to the substrate, wherein the third device is stacked onthe top side of the second device.
 20. The system of claim 16 wherein atleast a portion of the first device extends into the cavity region ofthe substrate.
 21. The system of claim 16, further comprising a thirddevice spaced apart from the first device and attached to the substrateat the cavity region.
 22. The system of claim 16 wherein the seconddevice attached to the base substrate at the perimeter region is a firstportion, and wherein the second device includes a second portionattached to the first device between the sidewalls of the cavity region.23. A method of forming a semiconductor device assembly, the methodcomprising: providing a base substrate having a cavity and a perimeterregion at least partially surrounding the cavity, wherein the cavityextends at least partially through the base substrate and has an openingwidth measured across opposing edges of the perimeter region; mounting afirst device in the cavity and attached to the base substrate at thecavity; and mounting a second device over at least a portion of thefirst device, extending across the opposing edges of the perimeterregion, and attached to the base substrate at the perimeter region,wherein the second device has a device width that is greater than theopening width of the cavity; wherein a top surface of the first deviceand a bottom surface of the second device are separated by a distancecorresponding to an air channel for cooling the first and second devicesvia convection.